Those obstacles have begun to play a pivotal role at the board level. In order to solve the signal integrity problem at the board level we needed a combination of tools that provided the most comprehensive board analysis solution. Here is how we selected the solution.

Where 10 years ago engineers at Siemens Information and Communications Network Systems were designing four- to six-layer boards with data rates well under 100 Mbits/second that were populated by components with multi-nanosecond edge rates. But today those same designers are building densely packed boards with up to 20 layers, speeds in excess of 600 Mbits/s and the latest high-speed components with rise and fall times in the hundreds of picoseconds. Subnanosecond edge rates and high-speed system clocks are forcing system designers to completely rethink their architectures to hurdle this new set of signal integrity, timing and EMI obstacles.

The increased routing density of modern designs has made signal integrity verification imperative because as ignals change layers or their proximity to neighboring signals they are exposed to varying levels of impedance mismatch. Moreover,many of these design issues are insidious. Since more common signal integrity problems such as overshoot and ringing are largely driven by IC driver strength and transition time,unannounced die shrinks or technology changes can easily push a proven design into a marginal performance range even when routing topologies have not changed. The impact can be catastrophic. Ringing can cause multiclocking of devices; overshoot can lead to timing errors and damaged components.

Manual approach outdated
Complicating the task has been a wholesale change in the way communications boards are constructed. Where once board designers could build a product line around an established and proven family of ICs and leverage the IC supplier's design guidelines, today that is rarely the case. While custom ASICs maximize performance and integration, they also often force board designers to take the time to perform their own measurements and manually solve signal integrity problems by tweaking place and route through multiple iterations of a design. In a competitive environment where time-to-market more often than not dictates product success, few design groups can afford that luxury.

Over the last decade as design complexity has sky-rocketed, it has become increasingly clear to Siemens design engineers that signal integrity analysis must be an integral part of the design flow to ensure design quality. In the mid-1990s the team's board design environment initially was built around a front end from Cadence Design Systems that interfaced to an in-house developed layout tool. Eventually, however,developers migrated to Mentor Graphics' Design Architect for their front end and the same company's Board Station product for printed-circuit-board design. A variety of verification and analysis tools were used for hardware/software cosimulation, thermal analysis and timing verification. Signal integrity issues were largely resolved on an ad hoc basis by manually refining likely problem areas.

With board complexity growing at a rapid rate -- some featured up to 5,000 signals and incorporated ASICs with more than 1,000 pins -- the manual development of design constraints that would ensure signal integrity quickly was becoming an untenable proposition. The unavailability of Spice models, their performance and functionality limitations when they were available and the absence of an interface to the host CAD system drove our engineers to consider a signal analysis tool that would simplify the signal integrity design process while offering state-of-the-art accuracy and speed. What we needed was a method capable of providing analysis across an entire board and able to quickly identify overshoot and undershoot problems, measure monotonicity for special classes, identify multithreshold crossing and perform comprehensive crosstalk analysis. The team's ultimate goal was to guarantee the electrical functionality of each board on the first pass of each design.

Crosstalk a high priority
Crosstalk was a particularly high-priority issue. As board densities escalated and data rates followed a similar upward spiral,the potential for board malfunctions due to crosstalk was growing as well. Identifying potential problems grew increasingly challenging as the designers grappled with a variety of signal-swing, etch-width,etch-spacing and receiver-susceptibility issues. Our engineers came to the conclusion that to solve these problems, they needed a tool that could calculate crosstalk across an entire board design and offer exact lossy line algorithms.

The tool had to simulate digital signals on a wide variety of pc boards and predict system-level noise and interconnect effects. It also had to perform a complete extraction of parametric data including inductance and capacitance matrices for crosstalk effects, insulator dielectrics loss, line resistance and skin-effect loss and provide reports to identify violations for signal delay, undershoot and overshoot, non-monotonic edges, incorrect loading and mismatched logic thresholds. Moreover, it had to support a wide variety of driver models including I/O Buffer Interface Specification (IBIS), Spice and custom-defined behavioral models.

No single tool
In any large, diverse organization with multiple ongoing development projects, no single tool suite can meet the needs of every design team. Certainly that has been the case at Siemens ICN. To meet our board analysis and routing requirements, approximately 80 percent of our design groups have turned to XTK, a suite of signal integrity tools from Innoveda Inc.(formerly Viewlogic Systems) coupled with the Specctra auto router, originally developed by Coopers & Chyan Technology and now sold by Cadence Design Systems. Our designers have generally found that this tool combination provides the most comprehensive board analysis solution available. Other designers have opted for Interconnect Synthesis, a board routing and analysis tool suite from Mentor Graphics.

While XTK offered an impressive array of capabilities, introducing it into the Siemens product development cycle did not come without some resistance. Our designers held a natural bias toward their established manual approach to resolving signal integrity matters. And it was clear from the outset that using XTK would not accelerate the layout process. In fact, its use would mean taking longer to finish the first layout of a design because the tool added a new level of analysis into our design cycle. Accordingly,the greatest challenge we faced was convincing the design team that by spending more time up front during layout using a signal integrity tool, it would end up saving time at the back end of the cycle by eliminating time-consuming reiterations of their design.

That concern was partially mitigated by gradually moving the signal integrity function up in the design process. Initially XTK was run only as part of our post-layout analysis. But we gradually discovered that the best way to avoid errors was to use the tool in the pre-layout stage. In fact, an early study found that when signal integrity was analyzed as part of post-layout analysis, our design team typically spent about a month per board detecting and fixing bugs. When we moved the signal integrity analysis to the prelayout phase, debug time dropped to less than two weeks.

Today, our designers use signal integrity analysis in prelayout to provide hardware developers with guidelines for their design. The team's goal is to perform the analysis during prelayout so the data can be used during placement to ensure that potential signal integrity problems are eliminated. Secondly, by integrating crosstalk algorithms into the routing process, we hoped to eventually use the signal integrity data to develop design constraints that would eliminate crosstalk as a potential issue.

Ensuring model accuracy
The biggest problem Siemens engineers have faced in implementing this signal integrity strategy has been the availability of accurate component models. Acquiring models early in the design flow is key to analyzing signal integrity before layout,a task that has become increasingly difficult as Siemens board designs have incorporated an increasing number of high-density ASICs. Moreover, very few silicon vendors provide IBIS models and those models that are available are often of marginal quality. Many design engineers today say they spend up to half their time obtaining, debugging and verifying simulation models.

To solve that problem,we created our own modeling group as part of our component engineering center. As component specialists, Siemens engineers acquire Spice models from vendors and build behavioral IBIS models from them. When IBIS models are available directly from vendors, they are checked for accuracy and syntax. For approximately 20 percent of the components that are not immediately available as Spice or IBIS models, the engineers make default models directly from measurements or data sheets. Usually models are compared with Spice simulation or measurement data to ensure accuracy. In this way, engineers at Siemens ICN have built their own extensive IBIS model library. Over the long term, Siemens hopes to offer its own expertise in modeling to silicon vendors so that it will one day be able to acquire accurate models early enough in the design flow.

One area in which the use of signal integrity analysis has proved to be unexpectedly useful has been in multiboard configurations. While we did not initially look at the multiboard capabilities when we selected a signal integrity tool, our group develops numerous multiboard solutions. For example, in a recent project designers simulated a backplane with two boards under development, two boards that had been previously developed and four DIMMs from three different vendors mounted onto one of the newer boards. To ensure that the configuration would perform as planned, the design team had to acquire three different databases from the DIMM vendors and simulate the entire configuration.

New level of complexity
One of the realities of pc-board design today is that while the migration to components with faster edge rates and higher-speed system clocks presents a wide variety of problems for designers of individual boards, it has also pushed multiboard system design to an entirely new level of complexity. Whereas subnanosecond edge rates may operate well within constraints within a single board, it is difficult to predict what will happen when they must interface to other boards in a system. And different multiboard configurations can have diverse impacts on issues such as system EMI and interconnect timing.

To solve problems such as these, we found the tool also needed to meet a number of additional requirements, such as supporting pc-board databases and performing system-wide analyses. It also had to provide prelayout analyses to help in the prototyping of critical clock and data network routing strategies. So far, we have relied on min/max modeling to help identify how variations in components and the environment would affect electrical performance and manufacturability. However, in the future Sweep and Monte Carlo analysis capabilities will be required.

Speed was also an issue. Large multiboard configurations typically involve significant processing overhead, so a high-performance tool was required to keep simulation times to a reasonable length. XTK's ability to perform simulations at speeds at least 100 times faster than Spice proved to be a very attractive capability.

Handsome payoff
Moving signal integrity analysis further up in the design cycle has paid off handsomely for Siemens. A recent in-house analysis found that doing it up front at the prelayout stage cut almost two weeks out of the average development cycle. And it has improved board performance as well. The study also determined that a 10 percent performance boost is possible simply by employing an automated signal integrity tool.

But perhaps its most impressive influence has been on board quality. Siemens engineers discovered they have eliminated one long-term failure in approximately every 5,000 boards by using signal integrity analysis and an in-house developed design-rule checker. At the same time, the number of redesigns has shrunk significantly. For every two boards designed, the study found our design teams were eliminating one respin. In fact, Siemens engineers have not designed a single board that has failed due to signal integrity problems in its first pass since bringing analysis on line. Ultimately our engineers have discovered that the payoff for investing in signal integrity analysis earlier in the design cycle -- higher quality and lower-cost boards due to fewer design turns -- has been well worth the effort.